Most microprocessor-based systems incorporate some form of ROM (Read-Only Memory) as a part of their basic memory system. Among other purposes, ROMs serve as "start-up" memory for a microprocessor system. Many large microprocessor-based systems rely on a disk drive or other mass-storage medium for storage of the bulk of their programming. These systems provide RAM (Random Access Memory) so that programs stored on disk may be copied into RAM for execution. However, RAM memory is volatile, that is, it does not retain its contents alter power is removed. Hence, such systems provide at least a small amount of "boot" ROM for system startup and basic system services (e.g., low-level device drivers, etc.).
Today's microprocessor systems tend, in increasing numbers, to be based upon wide-bus microprocessors, such as the Intel 80386 and 80486, and the Motorola 68040 microprocessors. These processors have 32 bit wide data and address buses. Most ROMs, however, come in 8 bit wide increments, for example, 32K.times.8 or 128K.times.8 (where 1K=1024). In order to provide ROM for wide bus microprocessors, it is necessary to either provide enough ROMs to cover the entire data bus width, (e.g., providing 128K bytes of memory in four 32K.times.8 ROMs, organized as a 32K.times.32 memory array) or to provide "byte funneling" or bus-width adaptation circuitry to interface between the wide-bus microprocessor and the relatively narrower bus of the ROM. In addition, address selection circuitry is required so that the ROM responds only to a specific set of addresses. Unfortunately, the economics of ROM memory chips are such that four 32K.times.8 ROMs are considerably more expensive than a single 128K.times.8 ROM, even though they provide the same amount of storage. This leads many system designers to opt for the cheaper memory and to provide bus-width adaptation.
In either case, a number of semiconductor device packages must be employed to incorporate ROM onto the local bus (i.e., directly connected to the microprocessor's unbuffered address, data, and control signals) of a wide bus microprocessor. If multiple individual ROM chips are used to provide a wide-format memory matched to the width of the microprocessor bus, then board space is required for those chips, and address decoding circuitry is still required. If a single ROM is used, then additional circuitry must be provided to adapt the bus width of the relatively narrow ROM to the wide bus width of the microprocessor.
A typical prior-art system of this type is shown in FIG. 1. A wide bus microprocessor (.mu.P) 105, such as the Intel Corp. 80486DX microprocessor, has an "n" bit local address bus 115, an "n " bit local data bus 120, and a local control bus 125 comprising a number of bus-control signals such as read and write strobe signals, etc., where "n" is equal to 32 for the Intel 80486DX. On a larger system, large numbers of peripheral devices and/or large amounts of memory may be expected to be attached to the microprocessor. In order to prevent the microprocessor's pin drivers (the circuits that drive the bus signals at each pin of the microprocessor) from becoming overloaded, an external bus interface 130 is provided. The external bus interface includes high-current driver chips capable of handling the relatively large signal loads imposed by large numbers of peripheral devices. Sometimes an external bus interface will impose "wait states" or idle cycles to be inserted into external bus activity so that external bus signals have adequate time to stabilize before they are used.
A single 128K.times.8 ROM memory 150 is interface to the microprocessor's (105) local bus via interface logic 140. The bus interface logic 140 interfaces with the microprocessor 105 address bus 115, data bus 120 and control signals 125, and provides an adapted 8 bit data bus 155, 17 bit address bus 160 and control signals 165 to the ROM.
When the microprocessor 105 attempts to read a 32-bit data word from the 8-bit wide ROM 150, the interface logic 140 must perform four 8 bit reads to consecutive addresses in the ROM 150, and assemble the four 8 bit responses into a 32-bit data word. This slows the microprocessor considerably when accessing the ROM memory.
In many modern PC systems, the external bus interface (e.g., 130) conforms to a specification commonly known as the "ISA" or Industry Standard Architecture. The ISA standard and similar bus interfaces include the aforementioned byte-gathering as a part of their standard functionality so that 8-bit peripherals and memory cards may be interfaced to wide-bus microprocessors. As a result, it is common practice to interface a BIOS ROM (e.g., 150) directly to the 8 bit interface within the external bus interface rather than to a dedicated interface circuit (e.g. 140), effectively placing the ROM on the external bus. Since external buses typically operate at lower speeds than local buses, (due in part to propagation delays in the external bus interface) this makes accesses to the ROM even slower than previously described.
In order to offset the effects of this slow ROM access, programmers will often copy the contents of a ROM into another high-speed local RAM memory and re-direct all calls to the ROM software over to the copies of the ROM software in RAM. This is known as ROM "shadowing". While this technique works, it ties up RAM memory space and complicates the design of both hardware and software.